1. Field of the Invention
The present invention relates to memory architectures for computer systems. More specifically, the present invention relates to a method and an apparatus for preserving the ordering of memory requests directed to multiple memory controllers.
2. Related Art
As computer systems grow increasingly more sophisticated, they are beginning to include multiple functional units. For example, it is common for a computer system to include one or more central processing units (CPUs) as well as a graphics processor and various DMA devices. As the number of functional units in a computer system increases, the computer system's memory comes under increasing pressure to service memory requests. Consequently, the memory can become a bottleneck to computer system performance.
One solution to this problem is to incorporate multiple memory channels in a computer system, wherein each memory channel handles accesses to a different region of memory. These multiple memory channels can work in parallel to service memory requests from the multiple functional units.
In designing a system with multiple memory channels, it is important to allow each functional unit to access to all of the memory channels, so that each functional unit can access all of the regions of memory. One problem in doing so is that memory requests from a given functional unit may return out of order from different memory controllers. This can create problems if there are dependencies between the memory requests. One solution to this problem is to provide additional circuitry at the functional unit to ensure that memory requests are executed in order. However, this complicates the design of the functional unit and may limit the performance advantages of queuing requests at memory controllers.
Another solution is to include circuitry within the memory controllers to ensure that requests from a given functional unit are issued in order. This simplifies the design of functional units and can improve overall computer system performance. However, this requires the memory controllers to communicate information with each other, which can cause prohibitively large communication delays.
What is needed is a method and an apparatus that enables multiple memory controllers to ensure that requests from functional units are issued in order without incurring large communication delays.